Trench gate technology is commonly used for improved break down voltage characteristics in semiconductor devices, especially high voltage devices. In the trench gate technology, the gate is vertically buried in the source, typically separated by an isolation cover. Other advantages of the trench gate technology include reduced junction gate field effect transistor (JFET) effect that may be undesirable at least in some applications. However, the trench gate technology does offer some disadvantages when lower voltage configurations are desired due to a need to reduce the width of the embedded gate. Reduced Surface Field (RESURF) technology is one of the most widely-used methods for the design of lateral high-voltage, low on-resistance devices. The technique has allowed the integration of high voltage devices, ranging from 20 V to 1200 V, with bipolar and MOS transistors.
TrenchMOS (Metal Oxide Semiconductor with trench gate) semiconductor devices are commonly used for power applications. A TrenchMOS device typically includes a semiconductor substrate having a layer of epitaxially grown, doped silicon located thereon, in which is formed a trench containing a gate electrode and gate dielectric. A source region of the device is located adjacent an upper part of the trench. The device also includes a drain region, which is separated from the source region by a body region, through which the trench extends.